I. Field of the Disclosure
The technology of the disclosure relates generally to memory systems, and particularly to detecting and preventing collisions of read and write operations within memory systems.
II. Background
Processor-based computer systems include memory for data storage. Different types of memory exist, each possessing certain unique features. For example, static random access memory (SRAM) is a type of memory that can be employed in processor-based computer systems. SRAM can store data without the need to periodically refresh the memory, unlike dynamic random access memory (DRAM) for example. An SRAM contains a plurality of SRAM bit cells (also referred to as “bit cells”) organized in rows and columns in an SRAM array. For any given row in an SRAM array, each column of the SRAM array includes an SRAM bit cell in which a single data value or bit is stored. Read and write operations are performed on a particular SRAM bit cell using read and write word lines which correspond to the SRAM bit cell row that includes the particular SRAM bit cell.
In this regard, some computer architectures allow read and write operations to be issued concurrently to an SRAM array to increase throughput performance of the memory. When a read and a write operation are issued concurrently to the same SRAM bit cell row in the SRAM array, an error may occur. This is known as a “read-write collision.” In a read-write collision, the write operation may begin writing data to the SRAM bit cell before the read operation is completed. Thus, the read operation may result in a read failure, as the data read from the SRAM bit cell may be an unknown value falling in-between the previously stored data and the newly written data. Notably, processor-based computer systems can employ circuits that are designed to detect and prevent read-write collisions in an SRAM array. However, circuits used to detect and prevent read-write collisions in an SRAM array commonly employ logic configured to detect read-write collisions prior to activation of a read word line. Because such logic is configured to detect read-write collisions prior to activation of the read word line, the logic generates overhead delays during each read operation, which decreases the read performance of the SRAM array.